1. Field of the Invention
The invention relates to a method of testing a mask pattern, and more particularly to a method of testing whether a mask pattern to which optical proximity-effect compensation is applied can be a base to form a desired resist pattern. The invention relates further to a program for causing a computer to carry out the above-mentioned method.
2. Description of the Related Art
Recent reduction in a design-rule of a semiconductor device causes a problem of optical proximity effect. Herein, optical proximity effect is defined as phenomenon in which a pattern different in shape from a mask pattern formed in a mask is formed on a resist. For instance, when a resist is exposed to a light through a mask having an L-shaped pattern, corners of an L-shaped pattern formed in a resist are rounded due to optical proximity effect. In addition, a width of a line pattern formed on a resist is dependent on an interval between line patterns due to optical proximity effect. For instance, a line pattern among line patterns formed in a high density and a line pattern solitarily formed would have widths different from each other on a resist, even if they had a common width on a mask.
In order to compensate for optical proximity effect, optical proximity-effect compensation is carried out during a fabrication process of a mask pattern. That is, a desired resist pattern is modified, taking optical interference into consideration, to thereby form a mask pattern. A desired resist pattern is transferred to a resist through a mask having the thus formed mask pattern. The thus formed mask pattern is different in shape from a desired resist pattern.
The optical proximity-effect compensation ensures a desired resist pattern, but causes necessity of testing a mask pattern by virtue of computer simulation. A shape of a resist pattern transferred from a mask having a certain mask pattern is dependent on interference of a light passing through the mask pattern. Definition of a resist pattern with such interference being taken into consideration cannot be accomplished without computer simulation. Hence, whether it is possible to form a desired resist pattern, based on a mask having a certain mask pattern, is tested by computer simulation.
In testing a mask pattern, it is important to be able to surely detect a non-desired resist pattern. For instance, Japanese Patent Application Publication No. 2000-214577 has suggested a method of detecting deformation of a pattern located remote from an edge of a pattern, in other words, detecting a resist pattern at a location where a resist pattern should not be formed, if a resist pattern is formed accurately in accordance with a designed pattern. The suggested method includes the steps of determining sampling points in a predetermined area other than an edge of a designed pattern, and comparing a dimension of a designed pattern with a dimension of a resist pattern calculated by simulation, at each of the sampling points. The suggested method makes it possible to detect deformation of a pattern in an area remote from an edge of a designed pattern, by selectively determining sampling points in a predetermined area other than an edge of a designed pattern.
It is preferable in a test of a mask pattern to determine a test standard, taking into consideration a structure of a semiconductor integrated circuit as a final product. Herein, a test standard is a standard in accordance with which a mask pattern is judged as to whether it is accurately formed. A decision as to whether a mask pattern is accurate is dependent on whether a resist pattern by which a semiconductor integrated circuit as a final product can properly operate is formed. Accordingly, a test standard is determined so as to make it possible to form a resist pattern by a semiconductor integrated circuit as a final product can properly operate.
When severe restriction is applied to a dimension of a resist pattern for properly operating a semiconductor integrated circuit, a test standard used for testing a mask pattern has to be determined accordingly. For instance, a width of a gate line in a MOS transistor much exerts an influence on characteristics of a MOS transistor. Accordingly, a width of a gate line has to be accurately controlled, and hence, a test standard used for testing a width of a resist pattern used as a mask through which a gate line is etched has to be determined accordingly. Furthermore, when a contact or a via-hole is designed to make contact with a wiring layer, the wiring layer has to be accurately positioned in order to ensure for the contact to make contact with the wiring layer, and hence, a position of a resist pattern used as a mask through which a wiring layer is etched has to be determined accordingly.
To the contrary, when a resist pattern has a broad dimensional margin in which a semiconductor integrated circuit can properly operate, it is not necessary to determine a severe test standard. This is because a severe test standard causes an increase in repair of a mask pattern with the result of an increase in a turn-around time (TAT) for fabricating a mask.
In addition, it is necessary to select sampling points at appropriate locations in testing a mask pattern, taking a structure of a semiconductor integrated circuit as a final product into consideration. In order to thoroughly test a mask pattern for surely detecting a non-desired resist pattern, it is effective to test a mask pattern with a lot of sampling points. However, a lot of sampling points would increase calculation necessary for carrying out simulation, resulting in that simulation takes much time. Accordingly, it is preferable that sampling points are selected only at appropriate locations, and a mask pattern is tested with a small number of sampling points.
As mentioned earlier, a semiconductor integrated circuit has portions in which a dimension of a pattern has to be accurately controlled, and portions in which it is not always necessary to accurately control a dimension of a pattern. Hence, it is preferable that a lot of sampling points are selected for the former portions, and a small number of sampling points are selected for the latter portions for making it possible to accurately test a mask pattern with a minimum number of sampling points.
Japanese Patent Application Publication No. 11-338904 has suggested a method of testing an error against a design rule, including the steps of arranging two cells adjacent to each other, removing patterns in the two cells which patterns are located at a first distance or more from tangential lines of the two cells, and detecting an error against a design rule in the rest of patterns of the two cells.
Japanese Patent Application Publication No. 11-96200 has suggested a semiconductor designer for detecting violation of a design rule in a mask layout pattern of a semiconductor integrated circuit, including means for inputting thereinto a layout-testing rule file in which layout data and layout design rule are written, means for recognizing a pattern to be tested in the layout data, means for calculating coordinates of a center of the thus recognized pattern, means for measuring a distance from the center to a predetermined point, means for comparing the thus measured distance to a reference distance written in the layout-testing rule file, and means for outputting an error when the distance does not meet with the reference distance.
Japanese Patent Application Publication No. 2000-294650 has suggested a method of testing a latch-up of layout data, including the steps of picking out a well region, a transistor region and a substrate contact region out of layout data of a semiconductor integrated circuit formed on a semiconductor substrate, and determining an over-size for each of the regions.